Cell Processing

A hydrogenated amorphous Si (a-Si:H) film, combined with a silicon nitride (SiNx:H) capping layer and a post-deposition anneal, can hugely enhance the surface passivation on crystalline silicon wafers. In this work, the influence of various deposition temperatures of a-Si:H films on the thermal stability of a-Si:H/SiNx:H stacks and a possible mechanism are discussed. Both minority carrier lifetime measurement and grazing-angle XRD were employed to study the thermal stability of a-Si:H/SiNx:H stacks, and the results are interpreted in terms of dihydrides concentration and epitaxial crystallization. With an appropriate thermal treatment, the a-Si:H film deposited at 130°C and capped by SiNx:H showed better passivation performance than 200°C-deposited a-Si:H/SiNx:H stacks, but under an excessive thermal budget the former showed more severe degradation of carrier lifetime. The more dihydride-rich composition within 130°C-deposited a-Si:H/SiNx:H stacks could be regarded as providing more effective intermediates for hydrogen interchanges, but on the other hand, it is also more susceptible to epitaxial crystallization.

A selective emitter is a doping layer that is heavily doped beneath the electrode and lightly doped in between the electrode grids. One of the disadvantages of conventional selective-emitter techniques is the need for a high phosphorus surface concentration to obtain low contact resistance and limit the shunts in the emitter. Effective emitter passivation below the contact is difficult because of the use of emitters with low sheet resistances and high doping concentrations. In this study, the selective emitter in the optimized light/light sheet-resistance combination was formed to reduce recombination under the metal contact. The fabrication of optimized light/light doped emitters was performed using a single-step diffusion process. Besides the benefit of low surface recombination for light/light combination, this approach also removes the need for a very precise alignment between the opened emitter pattern and the front screen-printed silver fingers. This work illustrates the achievement of an efficiency improvement of more than 0.4% absolute in large-scale production for selective emitter solar cells.

The workhorse of the photovoltaic industry, crystalline-silicon solar cells, continues to have additional headroom for conversion efficiency improvement as well as decreased production costs. As some companies have already demonstrated, clear pathways exist to bring about the achievement of >20%-efficient monocrystalline cells through the use of existing and novel production techniques. A newcomer to the solar cell and module sector, Suniva, has rapidly become a volume manufacturer using innovations originally developed at the University Center of Excellence in Photovoltaics (UCEP) at the Georgia Institute of Technology. This paper discusses the company’s first- and second-generation production technologies, including the implementation of ion implantation as a high-volume process, as well as details of cell-making approaches in the development stage.

Laser grooved buried contact (LGBC) solar cell technology is proving to be an attractive method of producing solar cells that are designed to operate at one sun and at concentration. Such technology is commercially available at Narec for applications at up to 100 suns. Although LGBC cells can have a higher efficiency at one sun when compared with standard non-selective emitter screen-printed solar cells, a more complex manufacturing process is required for these cells. This paper outlines the approach taken under the FP6 EU funded project “Lab2Line”, in which screen-printing and LGBC solar cell processing techniques are hybridized in order to produce lower cost, high efficiency solar cells.

Advanced Process Control (APC) has become an indispensable cornerstone of today’s semiconductor manufacturing. With roots in chemical processing, APC has not only proven itself in semiconductor manufacturing, but has potential to enhance yield in adjacent industries, such as photovoltaics. This paper gives a short introduction to APC, including its key elements, and proceeds to illustrate examples and success stories from the application of APC in semiconductor manufacturing. Based on these application examples, the lessons learned are summarized and the potentials of APC for PV are derived.

Solar cells are generally built in a process facility, often a turnkey line, where high throughput, minimum handling, and lowest cost are dominant factors. There are many complementary metal oxide semiconductor (CMOS) lines in the semiconductor industry – probably more than the number of turnkey lines – where yield, reliability, and device size and complexity are major issues, where millions of chips are made with very close tolerance, and the cost of importance is that of the finished chip. The possibility of using or converting a CMOS line for building Si solar cells has been considered by many in the past [2]. These lines have advantages such as sophisticated and highly developed automated equipment, frequent in-process metrology and quality control, and a high degree of flexibility as well as highly advanced shop floor control systems. The major disadvantages are cost and low throughput. This paper will discuss the differences, advantages, and disadvantages of CMOS and turnkey lines and show preliminary results for Si cells made in the CMOS line.

A recent spate of solar cell efficiency gains and record results underline the continued efforts to boost conversion efficiencies, which are at the core of reducing cost-per-watt goals. However, bringing such technology into the mainstream volume production world at little or no increase in manufacturing cost will prove more challenging. This paper takes a look at the current mainstream c-Si cell metallization efficiency developments that are starting to enter volume production with a promise of 20% cell efficiencies and low manufacturing costs.

Development of fine-line crystalline silicon solar cells is a potential direction for application of high-efficiency and low-cost solar cells in the industry. Fine-line mask-free metallization offers a great potential to increase cell efficiency by reducing metal shadowing losses and surface recombination losses. At China Sunergy, three promising approaches for fine-line crystalline silicon solar cells are currently undergoing research, including processes such as laser doping selective emitter (LDSE) technology, inkjet or aerosol jet printing of metal paste and upgraded screen-printing technology. This paper presents the basic investigations of these three manufacturing technologies, singling out the technology that presents the most potential for further application.

The emitter or p-n junction is the core of crystalline silicon solar cells. The vast majority of silicon cells are produced using a simple process of high temperature diffusion of dopants into the crystal lattice. This paper takes a closer look at the characteristics of this diffusion and possible variations in the process, and asks whether this step can lead to optimal emitters or whether emitters should be made with different processes in order to obtain the highest possible efficiency.

This paper, the third in a series covering cost of ownership (COO) studies for photovoltaics [1], examines the need for metallization of silicon-based solar cells and how it has evolved over the past few years. The technologies and techniques that are being developed for this part of cell manufacturing in the foreseeable future are also discussed. The paper will conclude with a COO case study using the DEK Solar PV3000 as an example.