Previously confined to the R&D labs and academic solar PV roadmaps, PERC based c-Si cell capacity upgrades are starting to have a tangible impact on the PV industry. By the end of 2014, ramped c-Si cell capacity based on the PERC concept will exceed 2.5GW.

This blog explains the drivers, the myths, the opportunities and the impact of PERC on PV CapEx and module performance. All data and figures shown in the blog are sourced from the NPD Solarbuzz PV Equipment Quarterly report, released July 2014.

Why PERC?

The Passivated Emitter and (locally diffused) Rear Contact (or PERC) solar cell acronym dates back to the 1980s at the University of New South Wales, at a time when a whole range of different advanced cell concepts were being researched. BP-Solar’s Saturn and Suntech’s Pluto cells also came from research at the University of New South Wales at the same time: in contrast to PERC, these concepts focused on selective emitter schemes on the front surface. PERC cells are part of a series of UNSW-coined passivated emitter based architectures.

Within the solar industry, putting a passivation layer (dielectric stacks) on the rear side of solar cells has typically been done previously only as a necessity, rather than a stand-alone enhancement. Once the surface-to-bulk area reaches a certain critical level, it becomes imperative to passivate the rear surface in order to reduce rear surface recombination velocities (losses).

While not quite so simplistic, this has essentially meant that only the thinnest wafers, or the very highest performance cells, have featured a passivation layer deposited on the rear side.

As a reference point, all mainstream (or ‘standard’) cells have passivation layers on the front side that act also as anti-reflection coatings. Historically, this was the segment that Centrotherm and Roth & Rau dominated for PECVD-based tool supply.

Therefore, rear-passivated cells (or PERC based variants) have for a long time featured extensively within most c-Si roadmaps discussed at PV conferences, in part because there was an expectation that wafer thicknesses would fall to below 120 microns. Added to this wafer reduction forecast was the concern that the pressure applied by screen-printing would become problematic on the thinner wafers, causing warping.

Another similar rear-surface passivated scheme – Laser Fired Contacts – was pushed with vigour by the Fraunhofer ISE some years back, and saw most European-based cell makers partner with local R&D institutes or even license the technology directly from ISE. The LFC technique had a number of advantages compared to PERC, but hit certain roadblocks, such as challenges in making good contact openings or not destroying the passivation layer during metallisation. Attempts to commercialise LFC were largely confined to Europe, with almost no appetite by the Chinese or Taiwanese cell makers to even trial within an R&D environment.

Polysilicon price declines put a halt on PERC

Back in the day, decreasing silicon costs (by continually using thinner wafers) was seen as one of the main routes to lowering overall module costs. However, this stopped abruptly when polysilicon spot prices plummeted during 2010 to 2012.

Essentially, this meant that there was no massive driver to move to thinner wafers. Cost reductions were almost free of charge by buying in lower cost wafers.

Therefore, rear side passivation techniques largely stayed at the research stage.

As the industry went into severe overcapacity mode at the midstream cell/module stage, the goal was firmly on cost-reduction while eking out any incremental efficiencies on offer. Ingot process improvements also became important to cell makers, with increased quality of multi-c-Si wafers being made available on the market almost every quarter.

Double/dual-printing set the tone first

In 2010, Applied Materials – as the dominant market-share supplier of back-end screen-printers – developed what is generally referred to as double-printing technology. There are several variants on the market, also known as dual-printing or print-on-print. Each essentially changes the legacy front finger printing process on standard c-Si cells, with thinner lines, higher aspect ratios and, critically, reduced silver consumption.

The efficiency increase for double-printing is marginal, but this is more than compensated by the cost reduction in silver paste usage: something that has become critical because polysilicon is no longer the dominant part of silicon and non-silicon module costs.

Double or dual-printing methods have become the de-facto components of most new c-Si line deliveries over the past couple of years, but have also seen extensive upgrade focus since 2011. About 50-60% of effective c-Si cell capacity is now double or dual-print capable, with the upgrade process still ongoing to retrofit other single-print cell lines in operation.

Improved front-side printing is also essential for most of the selective emitter schemes that were all the rage a few years back, with placement of the fingers needing to be monitored with accuracy. Previously, there was no need to have micron-level repeatability on front-side screen-printing. Having front-side printing tools already in place should make selective emitter upgrades in the future somewhat easier to do as a single process addition; more on this later in the blog with regards to ion implanting.

However, a key driver to the success of double/dual-printing upgrades was due to screen-printing tools being dominated by just a few suppliers, with the majority using Applied Materials’ Baccini equipment. ASYS and DEK-Solar also addressed the upgrade market quickly, with similar success, and have double/dual printing as standard on current offerings today.

The upgrade from single to double/dual printing is now routine and straightforward. This has been essential to this technology improvement taking off, as it did not require any great R&D know-how to be developed in-house by cell makers in China: something that ultimately prevented most of the selective emitter schemes from gaining traction.

Moving from front to back

To say that shifting the focus to improved rear side processing is a natural successor to front printing is somewhat naïve.

It is perhaps more relevant that most c-Si cell manufacturers fell into negative operating margin territory when end-market pricing collapsed due to overcapacity. Therefore, with a few exceptions, committing CapEx to new fabs was firmly off the table for some time.

Indeed, most Chinese c-Si manufacturers only increased wafer and cell tolling, or diverted any cash to funding downstream project activities.

Therefore, any low-risk route that can help increase module power ratings – without having to build new fabs – has taken on much greater emphasis. For the past two years, this has been provided simply by improvements to the bulk quality of multi c-Si wafers (due to directional solidification furnace optimisation), taking the pressure off cell manufacturers to make any changes other than moving to double/dual-printing.

The combination of improved multi c-Si wafer quality and double/dual-printing has been important in industry-standard multi c-Si cell panels moving from 245W to 265W ratings within three years. For example, a 25-acre solar farm specified a few years back and built today will see an increase of 0.4MWp-dc in rated capacity, much to the delight of project developers.

However, further big improvements in multi c-Si wafers are less likely today, compared to 12 months ago. Therefore, cell manufacturing now needs another boost, and one that can be done through a standard upgrade path within existing p-type mono and multi-cell lines.

This is where PERC enters the picture now.

Opportunities & challenges to PERC adoption

Virtually all ‘standard’ c-Si cells today use screen-printing for rear side metallisation (forming what is referred to as full-area aluminium Back Surface Field, or Al-BSF). Crucially however, this provides an inherent limitation to cell efficiency due to high rear surface recombination velocities.

Putting a passivation layer on the rear surface is now seen as a strong candidate for the next round of major cell capacity upgrades, much in the same way that double/dual-printing has been done on the front surface since 2010.

However, there are several challenges still to address for PERC cells:

  • Upgrades are mainly being focused on mono c-Si cells today. However, this is not PERC-specific, but simply because assessing process windows is easier on higher quality bulk material. Also, multi c-Si wafers have increased in quality, and it is possible that once mono process windows are fully understood, multi upgrades will follow mono line adoption.
  • There is no standard PERC method. Several variants (and discrete tool suppliers) are being investigated. These include: choice of passivation stack and capping layers, thickness of layers, screen-printing or PVD, ALD or PECVD, wet or dry etching for surface quality, etching or laser ablation for local contact openings, UV picosecond lasers or green nanosecond lasers, how to combine with front metallization; add to this European or Asian tool suppliers, and one-stop-shop purchasing or discrete supply-chain procurement
  • In contrast to Applied Materials’ role in making double-printing happen, in-house process knowledge at the cell manufacturing site is critical for widespread PERC cell adoption as part of a broader technology buy cycle.

However, there now appears to be a strong collective drive across Asian c-Si manufacturers, in particular Taiwan. As such, this is providing a collective cross-pollination of processing know-how: something that could easily propagate over to mainland China without too many barriers. Add in Korean and Southeast Asian cell manufacturing expertise and, regardless of the supply-chain dynamics, a critical mass could be accumulated to create an industry-wide knowledge base for PERC.

The rear passivation landscape

Analysing the c-Si ramped capacity for rear passivation layer-based lines (taken from the most recent release of the NPD Solarbuzz PV Equipment Quarterly database), we can see exactly what has been happening in PERC based capacity.

The attached figure tracks the ramped annual c-Si cell capacity that has passivation layers deployed on the rear side of the cell. The quarterly capacity figures are split into two parts to fully understand the status of PERC today.

The lower (blue) bar shows the thin/advanced c-Si cell capacity that uses rear side passivation by default. The upper (yellow) bar shows the PERC-specific capacity, mainly coming today from p-type mono c-Si cells. Within just two years, 2.5GW of PERC-specific ramped annual capacity has been added. Collectively, approximately 10% of the effective c-Si cell capacity today has rear side passivation layers applied.

Conclusions

We are still some way off from calling PERC the next de facto upgrade route for all p-type cell manufacturers, but the initial signs are encouraging. There are probably still about 12 months left to assess the performance output from the early adopters, and fully correlate fab capacity additions with module costs and productivity.

Given that the front-side double/dual-printing upgrade route is likely to take five years to go through its full cycle, PERC may well become the key focus for c-Si cell makers until 2017 or beyond. Other incremental efficiency/cost-reduction steps are likely to enter the mix, but these may simply add to the mainstream c-Si cell in five years that is front/rear-optimised based on p-type wafers.

Yes, there will be more n-type capacity addition. And probably some fresh attempts to try out selective emitters again. Additionally, ion implanters may also become another next-generation (front-end) cell upgrade for the front surface, running in parallel to PERC upgrades to the rear side.

Excluding the advanced cell concepts, the state-of-the-art p-type cell in five years could be based on high-quality multi (as close as multi can get to mono) wafers with ion-implanted mask-patterned selective emitters, double/dual-printed front-surface metallisation and PERC-based rear side formation.

The c-Si PV roadmap is gradually being reshaped by the cell producers and taking on a new market-driven route. PERC may well become a key element of this transformation which would be welcome news for PV equipment suppliers that have taken the brunt of the pause on greenfield fab developments over the past two years.

Lastly, the impact of the US trade war case should not be underestimated. This has had an immediate impact on Taiwan cell producers’ utilisation rates this quarter and likely will continue for a few months until Japan shipments fill the void ahead of 31 March 2015. Crucially, this creates a window of opportunity for Taiwan cell makers while fabs are being run at lower utilisation, to undertake upgrades. Previously, the focus was on making as many cells as possible to ship to modules that would end up in the US market, compliant with the 2012 US DoC ruling.

The PERC acronym is likely to see increased uptake within the PV vocabulary used in company press releases and conference call transcripts, as a sign of technology leadership. Ultimately however, we will be looking for firm details on line utilisation rates, average module ratings, CapEx and cost models before we can really say that PERC is fully established on the PV technology roadmap of the future.

PERC solar cell. Image: IMEC.

PERC solar cell. Image: IMEC.

PERC cell upgrades on standard c-Si cells have dramatically increased the capacity of cells featuring rear side passivation layers. Source: NPD Solarbuzz PV Equipment Quarterly report.

PERC cell upgrades on standard c-Si cells have dramatically increased the capacity of cells featuring rear side passivation layers. Source: NPD Solarbuzz PV Equipment Quarterly report.

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